By Xisheng Zhang and Mark C. Williams
Integrated System Design
Posted 09/05/01, 02:15:32 PM EDT

With the increased speed and complexity of the deep-submicron designs now being fabricated come new types of modeling issues that are proving beyond the grasp of the modeling techniques most commonly used today. In this article, we survey a number of the effects found in designs with feature sizes of 0.13 micron and below. We then present several new concepts to model some of the more critical effects found in today's state-of-the-art processes-giving the designer more tools to ensure first-pass success and time-to-market.

As device feature sizes continue to shrink, effects that were once ignored are now presenting challenges for analog and RF designers. These effects require new device-modeling techniques to predict the resulting circuit behavior. The table (page 53) lists deep-submicron MOSFET modeling issues now emerging and their effect on circuit operation. This article will focus on three of the critical problems: gate-resistance modeling for MOSFETs, on-chip inductor modeling and modeling the effect of process variation on interconnect parasitics.